レジスタ
code:sh
sim> help cpu registers
The CPU device implements these registers:
Name Size Purpose
-----------------------------
PC 15 program counter
AC 18 accumulator
L 1 link
MQ 18 multiplier-quotient
SC 6 shift counter
EAE_AC_SIGN 1 EAE AC sign
SR 18 front panel switches
ASW 15 address switches for RIM load
IORS 18 IORS register
CPU INT0:4 32 interrupt requests, 0:3 = API levels 0 to 3, 4 = PI level
INT_PEND 1 interrupt pending
ION 1 interrupt enable
ION_DELAY 2 interrupt enable delay
TRAPM 1 trap mode
TRAPP 1 trap pending
EXTM 1 extend mode
EXTM_INIT 1 exit mode value after reset
EMIRP 1 EMIR instruction pending
PCQ0:63 15 PC prior to last JMP, JMS, CAL or interrupt; most recent PC change first stop on
undefineds instruction
STOP_INST 1 stop on defined instruction
XCT_MAX 8 max numb of chained XCT's allowed
CPU WRU 8 interrupt character
sim>