チャタリングテスト用のカウンタ回路
SystemVerilogのソース
code:top.sv
module top(
input reset, btnU,
);
always_ff @(posedge reset, posedge btnU) begin
if (reset)
out_reg <= 0;
else if (btnU)
out_reg <= out_reg + 1;
end
assign led = out_reg;
endmodule
制約ファイル
code:chattering_test.xdc
# (※1)
## Switches
set_property PACKAGE_PIN V17 [get_ports {sw0}] set_property IOSTANDARD LVCMOS33 [get_ports {sw0}] set_property PACKAGE_PIN V16 [get_ports {sw1}] set_property IOSTANDARD LVCMOS33 [get_ports {sw1}] set_property PACKAGE_PIN W16 [get_ports {sw2}] set_property IOSTANDARD LVCMOS33 [get_ports {sw2}] set_property PACKAGE_PIN W17 [get_ports {sw3}] set_property IOSTANDARD LVCMOS33 [get_ports {sw3}] set_property PACKAGE_PIN W15 [get_ports {sw4}] set_property IOSTANDARD LVCMOS33 [get_ports {sw4}] set_property PACKAGE_PIN V15 [get_ports {sw5}] set_property IOSTANDARD LVCMOS33 [get_ports {sw5}] set_property PACKAGE_PIN W14 [get_ports {sw6}] set_property IOSTANDARD LVCMOS33 [get_ports {sw6}] set_property PACKAGE_PIN W13 [get_ports {sw7}] set_property IOSTANDARD LVCMOS33 [get_ports {sw7}] ## LEDs
set_property PACKAGE_PIN U16 [get_ports {led0}] set_property IOSTANDARD LVCMOS33 [get_ports {led0}] set_property PACKAGE_PIN E19 [get_ports {led1}] set_property IOSTANDARD LVCMOS33 [get_ports {led1}] set_property PACKAGE_PIN U19 [get_ports {led2}] set_property IOSTANDARD LVCMOS33 [get_ports {led2}] set_property PACKAGE_PIN V19 [get_ports {led3}] set_property IOSTANDARD LVCMOS33 [get_ports {led3}] set_property PACKAGE_PIN W18 [get_ports {led4}] set_property IOSTANDARD LVCMOS33 [get_ports {led4}] set_property PACKAGE_PIN U15 [get_ports {led5}] set_property IOSTANDARD LVCMOS33 [get_ports {led5}] set_property PACKAGE_PIN U14 [get_ports {led6}] set_property IOSTANDARD LVCMOS33 [get_ports {led6}] set_property PACKAGE_PIN V14 [get_ports {led7}] set_property IOSTANDARD LVCMOS33 [get_ports {led7}] ## Configuration options, can be used for all designs
(※1) ビルド時に以下のようなエラーが出たので、
Place 30-574 Poor placement for routing between an IO pin and BUFG. If this sub optimal condition is acceptable for this design, you may use the CLOCK_DEDICATED_ROUTE constraint in the .xdc file to demote this message to a WARNING. However, the use of this override is highly discouraged. These examples can be used directly in the .xdc file to override this clock rule. btnU_IBUF_inst (IBUF.O) is locked to IOB_X0Y15
and btnU_IBUF_BUFG_inst (BUFG.I) is provisionally placed by clockplacer on BUFGCTRL_X0Y0
chattering_test.xdcへエラーメッセージ通りに以下の制約を追加している。
code:xdc