VexRiscvのメモリバス

VexriscvのメモリバスはWishboneの模様。

code:litex-boards/build/radiona_ulx3s/gateware/radiona_ulx3s.v

VexRiscv VexRiscv(

// Inputs.

.clk (sys_clk),

.dBusWishbone_ACK (main_basesoc_dbus_ack),

.dBusWishbone_DAT_MISO (main_basesoc_dbus_dat_r),

.dBusWishbone_ERR (main_basesoc_dbus_err),

.externalInterruptArray (main_basesoc_interrupt),

.externalResetVector (main_basesoc_vexriscv),

.iBusWishbone_ACK (main_basesoc_ibus_ack),

.iBusWishbone_DAT_MISO (main_basesoc_ibus_dat_r),

.iBusWishbone_ERR (main_basesoc_ibus_err),

.reset ((sys_rst | main_basesoc_reset)),

.softwareInterrupt (1'd0),

.timerInterrupt (1'd0),

// Outputs.

.dBusWishbone_ADR (main_basesoc_dbus_adr),

.dBusWishbone_BTE (main_basesoc_dbus_bte),

.dBusWishbone_CTI (main_basesoc_dbus_cti),

.dBusWishbone_CYC (main_basesoc_dbus_cyc),

.dBusWishbone_DAT_MOSI (main_basesoc_dbus_dat_w),

.dBusWishbone_SEL (main_basesoc_dbus_sel),

.dBusWishbone_STB (main_basesoc_dbus_stb),

.dBusWishbone_WE (main_basesoc_dbus_we),

.iBusWishbone_ADR (main_basesoc_ibus_adr),

.iBusWishbone_BTE (main_basesoc_ibus_bte),

.iBusWishbone_CTI (main_basesoc_ibus_cti),

.iBusWishbone_CYC (main_basesoc_ibus_cyc),

.iBusWishbone_DAT_MOSI (main_basesoc_ibus_dat_w),

.iBusWishbone_SEL (main_basesoc_ibus_sel),

.iBusWishbone_STB (main_basesoc_ibus_stb),

.iBusWishbone_WE (main_basesoc_ibus_we)

);