CPUのバスインターフェース

PicoRV32

code:verilog

output mem_valid

output mem_instr

input mem_ready

output 31:0 mem_addr

output 31:0 mem_wdata

output 3:0 mem_wstrb

input 31:0 mem_rdata

FemtoRV

code:verilog

output 31:0 mem_addr, // address bus

output 31:0 mem_wdata, // data to be written

output 3:0 mem_wmask, // write mask for the 4 bytes of each word

input 31:0 mem_rdata, // input lines for both data and instr

output mem_rstrb, // active to initiate memory read (used by IO)

input mem_rbusy, // asserted if memory is busy reading value

input mem_wbusy, // asserted if memory is busy writing value