RISC-V interrupt enable
code: enable.asm
.align 4
.section .text
.global start
start:
csrr t0, mhartid
bnez t0, loop
li t0, (0b11 << 11) | (1 << 7) | (1 << 3)
csrw mstatus, t0
la t1, main
csrw mepc, t1
la t2, trap_vector
csrw mtvec, t2
li t3, (1 << 3) | (1 << 7) | (1 << 11)
csrw mie, t3
la ra, loop
mret
main:
sw t0, 0(zero)
ret
loop:
wfi
j loop
trap_vector:
addi a2, a2, 10
mret