HP Proliant Microserver の Modified BIOS 設定項目探索
このページは
HP Proliant MicroserverにModified BIOSをインストールしてゴニョゴニョしてLoad Optimal DefaultsをしたらWindows Server 2019 評価版がブルースクリーン(ACPI BIOS Error、エラーコード表示なし)で起動しなくなったので、対処のために妥当そうな設定項目をいろいろ調べた記録。 設定項目は他のLegacy AMI BIOSと共通(でなければ資料は出てこない)なので、他機種にも適用できる可能性。
参照先ページが非日本語の場合、編者は通常、Google翻訳を使って読んでいます。
2021年6月現在、このページは随時追記されます。
Quick Boot
Location: Main > Boot Settings Configuration
Default: Enabled
Splash Screen
Location: Main > Boot Settings Configuration
Default: Enabled
Bootup Num-Lock
Location: Main > Boot Settings Configuration
Default: Enabled
Restore after AC Power Loss
Location: Main > Boot Settings Configuration
Default: Last State
POST F1 Prompt
Location: Main > Boot Settings Configuration
Default: Delayed
評価: Delayedが最も穏健
Secure Virtual Machine Mode
Location: Advanced > CPU Configuration
Default: Enabled
評価: Enabledで良い。
Active Processor Cores
Location: Advanced > CPU Configuration
Default: All
Channel Interleaving
Location: Advanced > CPU Configuration
Default: Auto
評価: 追加機能に関するフラグなのでAutoで良さそう。
PowerNow
Location: Advanced > CPU Configuration
Default: Enabled
評価: 省電力機能なので起動には影響なさそう。Enabledで。
C1E Support
Location: Advanced > CPU Configuration
Default: Enabled
評価: 省電力機能なので起動には影響なさそう。Enabledで。
SATA Controller Mode
Location: Advanced > IDE Configuration
Default: AHCI
評価: OSがIDEを必要としないならAHCI又はRAIDで。
Embedded SATA Link Rate
Location: Advanced > IDE Configuration
Default: Auto
評価: 安定のためにはAuto、但しModified BIOSで拡張されたSATA4,5ポートを高速動作させるには3.0Gbps Maxで。
Drive Write Cache
Location: Advanced > IDE Configuration
Default: Disabled
評価: ハードウェアRAIDを使用している場合はこの値には意味がない。ストレージ内容の安全のためにはDisabledだが、パフォーマンスを求めるならEnabledで。
High Precision Event Timer
Location: Advanced > ACPI Configuration > Advanced ACPI Configuration
Default: Enabled
評価: 可用性のためにはEnabledだが、一部システムでパフォーマンスに影響するとの報告あり。
これをDisabledにしてもACPI BIOS Errorは解消しない。
WHEA Support
Location: Advanced > ACPI Configuration > General WHEA Configuration
Default: Enabled
評価: 追加機能なのでEnabledで問題ないんじゃなかろうか。
これをDisabledにしてもACPI BIOS Errorは解消しない。
AHCI BIOS Support
Location: Advanced > AHCI Configuration
Default: Enabled
参照ページが見つからない
評価: 自明なのでまぁいいか
View BMC System Event Log
Location: IPMI Configuration > SEL Configuration
Clear BMC System Event Log
Location: IPMI Configuration > SEL Configuration
BMC LAN Configuration
Location: IPMI Configuration > Set LAN Configuration
Default: DHCP
Parameter Selector
Location: IPMI Configuration > Set LAN Configuration > MAC Address
Default: 05
VLAN Support
Location: IPMI Configuration > Set LAN Configuration > VLAN Configuration
Default: Disabled
IPv6 Support
Location: IPMI Configuration > Set LAN Configuration > IPv6 Configuration
Default: Enabled
Auto Configuration
Location: IPMI Configuration > Set LAN Configuration > IPv6 Configuration
Default: Enabled
PEF Support
Location: IPMI Configuration > Set LAN Configuration > Set PEF Configuration
Default: Disabled
BMC Watch Dog Timer Action
Location: IPMI Configuration > Set LAN Configuration > Watchdog Configuration
Default: Reset System
BMC Watchdog Timeout
Location: IPMI Configuration > Set LAN Configuration > Watchdog Configuration
Default: 10 Min
MPS Revision
Location: Advanced > MPS Configuration
Default: 1.4
評価: OSは最新のを使うので1.4でいいけど、不安定だったら1.1を試してみようか。
Active State Power Management
Location: Advanced > PCI Express Configuration
Default: Disabled
評価: 安定性のためにはdisabledだが、PCIeカードが不安定にならないならenabledにしてもいいかも。
Embedded VGA Control
Location: Advanced > PCI Express Configuration
Default: Auto Detect
評価: リモートアクセスカードを使っている場合、Always Enabledにすると内蔵VGA端子からしか映像が出力されなくなる。逆にAuto DetectにするとリモートアクセスカードのVGA端子からしか映像が出力されなくなる。
PCTe Gen2
Location: Advanced > PCI Express Configuration
Default: GEN2
評価: GEN2でいいのでは。
VGA Momory Size
Location: Advanced > PCI Express Configuration
Default: 128MB
評価: UMAのメモリサイズ?
SMBIOS Smi Support
Location: Acvanced > SMBIOS Configuraion
Default: Enabled
評価: 「Optimal and Fail-Safe default settings: Enabled」
USB BIOS Support
Location: Advanced > USB Configuration
Default: Enabled
評価: レガシーUSBサポートの有無の設定らしい
BIOS EHCI Hand-Off
Location: Advanced > USB Configuration
Default: Enabled
評価: 「それ以降のオペレーティングシステムでは、通常EHCIハンドオフを無効にして実行します。」→Disabledがいいな。
Clear NVRAM
Location: PCIPnP
Default: No
help: Clear NVRAM during system boot.
Plug & Play O/S
Location: PCIPnP
Default: No
評価: 「Of course, all current motherboards now ship with the new ACPI BIOS. If you are using an ACPI-compliant operating system (i.e. Windows 98 and above) with an ACPI BIOS, then this PNP OS Installed feature is no longer relevant. 」→Noで。
PCI Latency Timer
Location: PCIPnP
Default: 64
評価: PCIExpressカードには関係ないし、デフォルトの64のままで良さそう。
Allocate IRQ to PCI VGA
Location: PCIPnP
Default: Yes
評価: PCIeはMSI割り込み使用なので関係ないのかなあ?
Palette Snooping
Location: PCIPnP
Default: Disabled
評価: 複数のPCIビデオカードを使用していなければEnabledで問題ないのかなあ。
PCI IDE BusMaster
Location: PCIPnP
Default: Disabled
評価: 参照先ページがリコメンドしているのでEnabledで。
Offboard PCI/ISA IDE Card
Location: PCIPnP
Default: Auto
評価: 複数のPCI IDEカードを使っていなければautoで問題なさそう。
IRQ3,4,5,7,9,10,11,14,15
Location: PCIPnP
Default: Available
DMA Channel 0,1,3,5,6,7
Location: PCIPnP
Default: Available
Reserved Momory Size
Location: PCIPnP
Default: Disabled
1st,2nd,3rd Boot Device
Location: Boot > Boot Device Priority
1st,2nd Drive
Location: Boot > Hard Disk Drives
1st Drive
Location: Boot > Removable Drives
Change Admin Password
Location: Security
Bank Interleaving
Location: Chipset > NorthBridge Configuration > Memory Configuration
Default: Auto
Channel Interleaving
Location: Chipset > NorthBridge Configuration > Memory Configuration
Default: Auto
Enable Clock to All DIMMs
Location: Chipset > NorthBridge Configuration > Memory Configuration
Default: Disabled
Help: Enable Unused Clocks to DIMMs Even Memory Slots are NOT populated
評価: 電力削減に関係するだけならばDisabledのままでも良さそう。
CS Sparing Enable
Location: Chipset > NorthBridge Configuration > Memory Configuration
Default: DIsabled
Help: Reserve a spare memory rank in each node.
評価: メモリスペアリングのことならばEnabledにしなくてもOSの起動に支障はなさそう。メモリに異常があるならばスペアリングに頼るのではなくメモリを交換すべき。
Power Down Enable
Location: Chipset > NorthBridge Configuration > Memory Configuration
Default: Auto
Help: Enable or disable DDR power down mode.
評価: パワーダウンモードDisabledのほうがOSの起動可能性は高くなるような気がする。
Power Down Mode
Location: Chipset > NorthBridge Configuration > Memory Configuration
Default: Auto
DRAM Parity Enable
Location: Chipset > NorthBridge Configuration > Memory Configuration
Default: Auto
評価: パリティはECCとは異なるらしい。
Bank Swizzle Mode
Location: Chipset > NorthBridge Configuration > Memory Configuration
Default: Auto
評価: 安定性を重んじるならDisableを試してみる。
DRAM Timing Config
Location: Chipset > NorthBridge Configuration > DRAM Timing Configuration
Default: Auto
TRAS
Location: Chipset > NorthBridge Configuration > DRAM Timing Configuration
Default: Message Format Ver
HT Link Width Control
Location: Chipset > NorthBridge Configuration
Default: Enable
GFxNBPstateDis Support
Location: Chipset > NorthBridge Configuration
Default: Disabled
T0Time Override
Location: Chipset > NorthBridge Configuration
Default: Disabled
Internal Graphics Mode
Location: Chipset > NorthBridge2 Configuration > Internal Graphics Configuration
Default: UMA
GFX Engine Clock Override
Location: Chipset > NorthBridge2 Configuration > Internal Graphics Configuration
Default: Disable
Special Graphics Features
Location: Chipset > NorthBridge2 Configuration > Internal Graphics Configuration
Default: Disabled
State: Glay out
FB Location
Location: Chipset > NorthBridge2 Configuration > Internal Graphics Configuration
Default: Below 4G
Lanes 0-3,4-7,8-11,12-15
Location: Chipset > NorthBridge2 Configuration > Internal Graphics Configuration
Default: Disable
AMD 880 HD Audio
Location: Chipset > NorthBridge2 Configuration > Internal Graphics Configuration
Default: Disabled
Bank Mapping Control
Location: Chipset > NorthBridge2 Configuration > Internal Graphics Configuration > Debug Option
Default: Auto
UMA Address Swizzle Control
Location: Chipset > NorthBridge2 Configuration > Internal Graphics Configuration > Debug Option
Default: Auto
Video Display Devices
Location: Chipset > NorthBridge2 Configuration > Internal Graphics Configuration
Default: Auto
TV Standard
Location: Chipset > NorthBridge2 Configuration > Internal Graphics Configuration
Default: NTSC
Expansion Mode
Location: Chipset > NorthBridge2 Configuration > Internal Graphics Configuration
Default: Enabled
GFX Dual Slot Configuration
Location: Chipset > NorthBridge2 Configuration > PCI Express Configuration
Default: Disabled
GPP Slots Power Limit, W
Location: Chipset > NorthBridge2 Configuration > PCI Express Configuration
Default: 256
Gen2 High Speed Mode
Location: Chipset > NorthBridge2 Configuration > PCI Express Configuration > Port #02 Features Default: Disabled
Link ASPM
Location: Chipset > NorthBridge2 Configuration > PCI Express Configuration > Port #02 Features Default: Disabled
Location: Chipset > NorthBridge2 Configuration > PCI Express Configuration > Port #02 Features Default: Disabled
Slot Power Limit, W
Location: Chipset > NorthBridge2 Configuration > PCI Express Configuration > Port #02 Features Default: 256
Location: Chipset > NorthBridge2 Configuration > PCI Express Configuration
State: No Settings
NB-SB Link ASPM
Location: Chipset > NorthBridge2 Configuration > PCI Express Configuration > NB-SB Port Features
Default: L1
NP NB-SB VC1 Traffic Support
Location: Chipset > NorthBridge2 Configuration > PCI Express Configuration > NB-SB Port Features
Default: Disabled
Link Width
Location: Chipset > NorthBridge2 Configuration > PCI Express Configuration > NB-SB Port Features
Default: Auto
NB Power Management Features
Location: Chipset > NorthBridge2 Configuration
Default: Auto
Memory Hole
Location: Chipset > NorthBridge2 Configuration
Default: Disabled
SB GPP Port Configuration (Section)
Location: Chipset > SouthBridge Configuration
SB GPP Function
Location: Chipset > SouthBridge Configuration > SB GPP Port Configuration
Default: Disable
GPP Rane Reversal
Location: Chipset > SouthBridge Configuration > SB GPP Port Configuration
Default: Disabled
NB-SB PHY PLL Power Down
Location: Chipset > SouthBridge Configuration > SB GPP Port Configuration
Default: Enable
HD Audio Azalia Device
Location: Chipset > SouthBridge Configuration > SB Azalia Audio Configuration
Default: Disabled
Azalia Front Panel
Location: Chipset > SouthBridge Configuration > SB Azalia Audio Configuration
Default: Auto
OHCI HC(Bus 0 Dev 18 Fn 0)
Location: Chipset > SouthBridge Configuration > SB USB Configuration
Default: Enabled
EHCI HC(Bus0 Dev 18 Fn 2)
Location: Chipset > SouthBridge Configuration > SB USB Configuration
Default: Enabled
OHCI HC(Bus 0 Dev 19 Func 0)
Location: Chipset > SouthBridge Configuration > SB USB Configuration
Default: Enabled
EHCI HC(Bus 0 Dev 19 Fn 2)
Location: Chipset > SouthBridge Configuration > SB USB Configuration
Default: Enabled
OHCI HC(Bus0 Dev 22 Func 0)
Location: Chipset > SouthBridge Configuration > SB USB Configuration
Default: Enabled
EHCI HC(Bus 0 Dev 22 Fn 2)
Location: Chipset > SouthBridge Configuration > SB USB Configuration
Default: Enabled
OHCI HC(Bus 0 Dev 20 Fn 5)
Location: Chipset > SouthBridge Configuration > SB USB Configuration
Default: Disabled
OnChip SATA Channel
Location: Chipset > SouthBridge Configuration > SB SATA Configuration
Default: Enabled
OnChip IDE Type
Location: Chipset > SouthBridge Configuration > SB SATA Configuration
Default: Legacy IDE
SATA IDE Combined Mode
Location: Chipset > SouthBridge Configuration > SB SATA Configuration
Default: Enabled
PATA Channel Config
Location: Chipset > SouthBridge Configuration > SB SATA Configuration
Default: SATA as primary
SATA ESP on all PORT
Location: Chipset > SouthBridge Configuration > SB SATA Configuration
Default: Disabled
SATA Power on all PORT
Location: Chipset > SouthBridge Configuration > SB SATA Configuration
Default: Enabled
In-Chip NIC
Location: Chipset > SouthBridge Configuration > SB GEC Configuration
Default: Enabled
GEC Resume Wake from S5
Location: Chipset > SouthBridge Configuration > SB GEC Configuration
Default: Disabled
GEC OPROM
Location: Chipset > SouthBridge Configuration > SB GEC Configuration
Default: Disabled
CPU Reset on Sync_Flood
Location: Chipset > SouthBridge Configuration > SB Debug Configuration
Default: Enabled
SPI Speed
Location: Chipset > SouthBridge Configuration > SB Debug Configuration
Default: 33MHz
SPI Fast Read Enable
Location: Chipset > SouthBridge Configuration > SB Debug Configuration
Default: Disabled
USB Msi Option
Location: Chipset > SouthBridge Configuration > SB Debug Configuration
Default: Disabled
Azalia Msi Option
Location: Chipset > SouthBridge Configuration > SB Debug Configuration
Default: Disabled
LPC Msi Option
Location: Chipset > SouthBridge Configuration > SB Debug Configuration
Default: Disabled
PCIB Msi Option
Location: Chipset > SouthBridge Configuration > SB Debug Configuration
Default: Disabled
AB Msi Option
Location: Chipset > SouthBridge Configuration > SB Debug Configuration
Default: Disabled
EC ROM Protection
Location: Chipset > SouthBridge Configuration > SB Debug Configuration
Default: Enabled
SB Spread Spectrum
Location: Chipset > SouthBridge Configuration > SB Debug Configuration
Default: Disabled
NB SB GEN2
Location: Chipset > SouthBridge Configuration > SB Debug Configuration
Default: Enabled
SB GPP GEN2
Location: Chipset > SouthBridge Configuration > SB Debug Configuration
Default: Disabled
SB GPP COMPLIANCE
Location: Chipset > SouthBridge Configuration > SB Debug Configuration
Default: Disabled
GPP MEM WR IMPROVE
Location: Chipset > SouthBridge Configuration > SB Debug Configuration
Default: Enabled
A12 SBPCIe OrderRule
Location: Chipset > SouthBridge Configuration > SB Debug Configuration
Default: Enabled
SB02123 Workaround
Location: Chipset > SouthBridge Configuration > SB Debug Configuration
Default: Enabled
Location: Chipset > SouthBridge Configuration > SB Debug Configuration
Default: Enabled
USB Phy Power Down
Location: Chipset > SouthBridge Configuration > SB Debug Configuration
Default: Disabled
PCIB Arbiter 2
Location: Chipset > SouthBridge Configuration > SB Debug Configuration
Default: Disabled
_OSC for PCI0
Location: Chipset > SouthBridge Configuration > SB Debug Configuration
Default: Enabled
GEC PHY Status
Location: Chipset > SouthBridge Configuration > SB Debug Configuration
Default: Gb PHY Mode
SB GEC Powered down Policy
Location: Chipset > SouthBridge Configuration > SB Debug Configuration
Default: Never pwoered dow
GEC Debug Bus
Location: Chipset > SouthBridge Configuration > SB Debug Configuration
Default: Disabled
GEC ROM Protection
Location: Chipset > SouthBridge Configuration > SB Debug Configuration
Default: Enabled
PCI CLK 0,1,2,3,4
Location: Chipset > SouthBridge Configuration > SB Debug Configuration
Default: Enabled
SATA Set MaxGen2 Capability
Location: Chipset > SouthBridge Configuration > SB Debug Configuration
Default: Enabled
SATA PHY Ref Clock
Location: Chipset > SouthBridge Configuration > SB Debug Configuration
Default: Int 100MHz
Aggressive Link PM Capability
Location: Chipset > SouthBridge Configuration > SB Debug Configuration
Default: Enabled
Port Multiplier Capability
Location: Chipset > SouthBridge Configuration > SB Debug Configuration
Default: Enabled
Partial State Capability
Location: Chipset > SouthBridge Configuration > SB Debug Configuration
Default: Enabled
Slumber State Capability
Location: Chipset > SouthBridge Configuration > SB Debug Configuration
Default: Enabled
BIOS/OS Handoff Cap
Location: Chipset > SouthBridge Configuration > SB Debug Configuration
Default: Disabled
SATA Ports Hot Plug Capability
Location: Chipset > SouthBridge Configuration > SB Debug Configuration
Default: Enabled
Unused SATA Port Auto Shut Dow
Location: Chipset > SouthBridge Configuration > SB Debug Configuration
Default: Disable
Options for FIS-based Switchin
Location: Chipset > SouthBridge Configuration > SB Debug Configuration
Default: Disabled
Command Completion Coalescing
Location: Chipset > SouthBridge Configuration > SB Debug Configuration
Default: Disabled
SATA MSI Capability
Location: Chipset > SouthBridge Configuration > SB Debug Configuration
Default: Enabled
In-Chip IR
Location: Chipset > SouthBridge Configuration
Default: Disabled
Thermal Fan Control
Location: Chipset > SouthBridge Configuration
Default: Enable
Atheros AR8132M NIC
Location: Chipset > OnBoard Peripherals Configuration
Default: Enable
AR8132M NIC Option ROM
Location: Chipset > OnBoard Peripherals Configuration
Default: Disabled
NEC USB3.0 Controller
Location: Chipset > OnBoard Peripherals Configuration
Default: Enable
(2021-06-12)(2021-06-25)(2021-06-27)